Verification Engineer-vlsi Share to social media (0-3 yrs)

smartchipdesign – Bangalore, Karnataka

verilog,vlsi,systemverilog,ovm,uvm

Job description Experience: Min 0 -3 yearsCandidate should have experience on some large projects in Formal Verification.Domain knowledge in processors will be an added advantage.Experience in normal verification methodologies is an added advantageExperience in C/C / scripting is an added advantage. vlsi, C/C++, scripting